View M48T58Y-70PC1_6680777.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

august 2010 doc id 2412 rev 7 1/33 1 m48t58 m48t58y 5.0 v, 64 kbit (8 kb x 8) timekeeper ? sram features integrated, ultra low power sram, real-time clock, power-fail control circuit and battery bytewide ? ram-like clock access bcd coded year, month, day, date, hours, minutes, and seconds frequency test output for real-time clock automatic power-fail chip deselect and write protection write protect voltages (v pfd = power-fail deselect voltage): ?m48t58: v cc = 4.75 to 5.5 v 4.5 v v pfd 4.75 v ?m48t58y: v cc = 4.5 to 5.5 v 4.2 v v pfd 4.5 v self-contained battery and crystal in the caphat ? dip package packaging includes a 28-lead soic and snaphat ? top (to be ordered separately) soic package provides direct connection for a snaphat housing containing the battery and crystal pin and function compatible with jedec standard 8 kb x 8 srams rohs compliant ? lead-free second level interconnect 2 8 1 2 8 1 pcdip28 (pc) battery/crystal caphat? snaphat ? (sh) battery/crystal soh28 (mh) www.st.com
contents m48t58, m48t58y 2/33 doc id 2412 rev 7 contents 1 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 2 operation modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 3 read mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 4 write mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 5 data retention mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 6 clock operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 6.1 reading the clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 6.2 setting the clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 6.3 stopping and starting the oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 6.4 calibrating the clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 6.5 battery low flag . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 6.6 century bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 6.7 v cc noise and negative going transients . . . . . . . . . . . . . . . . . . . . . . . . . 20 7 maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 8 dc and ac parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 9 package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 10 part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 11 environmental information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 12 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
m48t58, m48t58y list of tables doc id 2412 rev 7 3/33 list of tables table 1. signal names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 table 2. operating modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 table 3. read mode ac characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 table 4. write mode ac characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 3 table 5. register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 table 6. absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 table 7. operating and ac measurement conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 table 8. capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 table 9. dc characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 table 10. power down/up ac characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 table 11. power down/up trip points dc characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 table 12. pcdip28 ? 28-pin plastic dip, battery caphat?, package mech. data . . . . . . . . . . . . . 25 table 13. soh28 ? 28-lead plastic small outline, 4-socket battery snaphat ? , package mech. data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 table 14. sh ? 4-pin snaphat ? housing for 48 mah battery & crystal, package mech. data . . . . . 27 table 15. sh ? 4-pin snaphat ? housing for 120 mah battery & crystal, package mech. data . . . . 28 table 16. ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 table 17. snaphat ? battery table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 table 18. document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
list of figures m48t58, m48t58y 4/33 doc id 2412 rev 7 list of figures figure 1. logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 figure 2. dip connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 figure 3. soic connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 figure 4. block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 figure 5. read mode ac waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 figure 6. write enable controlled, write ac waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 figure 7. chip enable controlled, write ac waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 figure 8. crystal accuracy across temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 8 figure 9. clock calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 figure 10. supply voltage protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 figure 11. ac measurement load circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 figure 12. power down/up mode ac waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 figure 13. pcdip28 ? 28-pin plastic dip, battery caphat?, package outline . . . . . . . . . . . . . . . . . 25 figure 14. soh28 ? 28-lead plastic small outline, 4-socket battery snaphat ? , package outline . . . 26 figure 15. sh ? 4-pin snaphat ? housing for 48 mah battery & crystal, pack. outline . . . . . . . . . . . 27 figure 16. sh ? 4-pin snaphat ? housing for 120 mah battery & crystal, package outline. . . . . . . . 28 figure 17. recycling symbols . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
m48t58, m48t58y description doc id 2412 rev 7 5/33 1 description the m48t58/y timekeeper ? ram is a 8 kb x 8 non-volat ile static ram and real-time clock. the monolithic chip is available in two special packages to provide a highly integrated battery-backed memory and real-time clock solution. the m48t58/y is a non-volatile pin and function equivalent to any jedec standard 8b kb x 8 sram. it also easily fits in to many rom, eprom, and eeprom sockets, providing the non-volatility of proms without any requirement for special write timing or limitations on the number of writes that can be performed. the 28-pin, 600 mil dip caphat ? houses the m48t58/y silicon with a quartz crystal and a long life lithium button cell in a single package. the 28-pin, 330 mil soic provides sockets with gold plated contacts at both ends for direct connection to a separate snaphat ? housing containing the battery and crystal. the unique design allows the snaphat battery package to be mounted on top of the soic package after the completion of the surface mount process. insertion of the snaphat housing after reflow prevents potential battery and crystal damage due to the high temperatures required for device surface-mounting. the snaphat housing is keyed to prevent reverse insertion. the soic and battery/crystal packages are shipped separately in plastic anti-static tubes or in tape & reel form. for the 28-lead soic, the battery/crystal package (e.g., snaphat) part number is ?m4t28- br12sh?. figure 1. logic diagram ai01 3 74b 1 3 a0-a12 w dq0-dq7 v cc m4 8 t5 8 m4 8 t5 8 y g e2 v ss 8 e1 ft
description m48t58, m48t58y 6/33 doc id 2412 rev 7 table 1. signal names figure 2. dip connections figure 3. soic connections a0-a12 address inputs dq0-dq7 data inputs / outputs ft frequency test output (open drain) e1 chip enable 1 e2 chip enable 2 g output enable w write enable v cc supply voltage v ss ground a1 a0 dq0 a7 a4 a 3 a2 a6 a5 e2 a10 a 8 a9 dq7 w a11 g e1 dq5 dq1 dq2 dq 3 v ss dq4 dq6 a12 ft v cc ai01 3 75b m4 8 t5 8 m4 8 t5 8 y 8 1 2 3 4 5 6 7 9 10 11 12 1 3 14 16 15 2 8 27 26 25 24 2 3 22 21 20 19 1 8 17 ai01 3 76b 8 2 3 4 5 6 7 9 10 11 12 1 3 14 22 21 20 19 1 8 17 16 15 2 8 27 26 25 24 2 3 1 a1 a0 dq0 a7 a4 a 3 a2 a6 a5 e2 a10 a 8 a9 dq7 w a11 g e1 dq5 dq1 dq2 dq 3 v ss dq4 dq6 a12 ft v cc m4 8 t5 8 y
m48t58, m48t58y description doc id 2412 rev 7 7/33 figure 4. block diagram ai01377c lithium cell oscillator and clock chain v pfd ft v cc v ss 32,768 hz crystal voltage sense and switching circuitry 8 x 8 biport sram array 8184 x 8 sram array a0-a12 dq0-dq7 e1 e2 w g power
operation modes m48t58, m48t58y 8/33 doc id 2412 rev 7 2 operation modes as figure 4 on page 7 shows, the static memory array and the quartz controlled clock oscillator of the m48t58/y ar e integrated on one silicon chip. the two circuits are interconnected at the upper eight memory locations to provide user accessible bytewide? clock information in the bytes with addresses 1ff8h-1fffh. the clock locations contain the century, year, month, date, day, hour, minute, and second in 24 hour bcd format (except for the century). corrections for 28, 29 (leap year - valid until 2100), 30, and 31 day months are made automatically. byte 1ff8h is the clock control register. this byte controls user access to the clock information and also stores the clock calibration setting. the eight clock bytes are not the actual clock counters themselves; they are memory locations consisting of biport? read/write memory cells. the m48t58/y includes a clock control circuit which updates the clock bytes with current information once per second. the information can be accessed by the user in the same manner as any other location in the static memory array. the m48t58/y also has its own power-fail detect circuit. the control circuitry constantly monitors the single 5 v supply for an out-of-tolerance condition. when v cc is out of tolerance, the circuit write protects the sram, providing a high degree of data security in the midst of unpredictable system operation brought on by low v cc . as v cc falls below the battery backup switchover voltage (v so ), the control circuitry connects the battery which maintains data and clock operat ion until valid power returns. table 2. operating modes note: x = v ih or v il ; v so = battery backup switchover voltage. mode v cc e1 e2 g w dq0-dq7 power deselect 4.75 to 5.5 v or 4.5 to 5.5 v v ih xxxhigh z standby deselect x v il x x high z standby write v il v ih xv il d in active read v il v ih v il v ih d out active read v il v ih v ih v ih high z active deselect v so to v pfd (min) (1) 1. see table 11 on page 24 for details. x x x x high z cmos standby deselect v so (1) x x x x high z battery backup mode
m48t58, m48t58y read mode doc id 2412 rev 7 9/33 3 read mode the m48t58/y is in the read mode whenever w (write enable) is high, e1 (chip enable 1) is low, and e2 (chip enable 2) is high. the unique address specified by the 13 address inputs defines which one of the 8,192 bytes of data is to be accessed. valid data will be available at the data i/o pins within address access time (t avqv ) after the last address input signal is stable, providing that the e1 , e2, and g access times are also satisfied. if the e1 , e2 and g access times are not met, va lid data will be available afte r the latter of the chip enable access times (t e1lqv or t e2hqv ) or output enable access time (t glqv ). the state of the eight three-state data i/o signals is controlled by e1 , e2 and g . if the outputs are activated before t avqv , the data lines will be driven to an indeterminate state until t avqv . if the address inputs are changed while e1 , e2 and g remain active, output data will remain valid for outp ut data hold time (t axqx ) but will go indeterm inate until the next address access. figure 5. read mode ac waveforms note: write enable (w ) = high. ai00962 tavav tavqv taxqx te1lqv te1lqx te1hqz tglqv tglqx tghqz valid a0-a12 e1 g dq0-dq7 te2hqv te2hqx valid te2lqz e2
read mode m48t58, m48t58y 10/33 doc id 2412 rev 7 table 3. read mode ac characteristics symbol parameter (1) 1. valid for ambient operating temperature: t a = 0 to 70 c; v cc = 4.75 to 5.5 v or 4.5 to 5.5 v (except where noted). m48t58/y unit min max t avav read cycle time 70 ns t avqv address valid to output valid 70 ns t e1lqv chip enable 1 low to output valid 70 ns t e2hqv chip enable 2 high to output valid 70 ns t glqv output enable low to output valid 35 ns t e1lqx (2) 2. c l = 5 pf. chip enable 1 low to output transition 5 ns t e2hqx (2) chip enable 2 high to output transition 5 ns t glqx (2) output enable low to output transition 5 ns t e1hqz (2) chip enable 1 high to output hi-z 25 ns t e2lqz (2) chip enable 2 low to output hi-z 25 ns t ghqz (2) output enable high to output hi-z 25 ns t axqx address transition to output transition 10 ns
m48t58, m48t58y write mode doc id 2412 rev 7 11/33 4 write mode the m48t58/y is in the write mode whenever w and e1 are low and e2 is high. the start of a write is referenced from th e latter occurring falling edge of w or e1 , or the rising edge of e2. a write is terminated by the earlier rising edge of w or e1 , or the falling edge of e2. the addresses must be held valid throughout the cycle. e1 or w must return high or e2 low for a minimum of t e1hax or t e2lax from chip enable or t whax from write enable prior to the initiation of another read or write cycle. data-in must be valid t dvwh prior to the end of write and remain valid for t whdx afterward. g should be kept high during write cycles to avoid bus contention; although, if the output bus has been activated by a low on e1 and g and a high on e2, a low on w will disable the outputs t wlqz after w falls. figure 6. write enable controlled, write ac waveform ai0096 3 tavav twhax tdvwh data input a0-a12 e1 w dq0-dq7 valid e2 tavwh tave1l tave2h twlwh tavwl twlqz twhdx twhqx
write mode m48t58, m48t58y 12/33 doc id 2412 rev 7 figure 7. chip enable controlled, write ac waveforms ai00964b tavav te1hax tdve1h tdve2l a0-a12 e1 w dq0-dq7 valid e2 tave1h tave1l tavwl tave2l te1le1h te2lax tave2h te2he2l te1hdx te2ldx data input
m48t58, m48t58y write mode doc id 2412 rev 7 13/33 table 4. write mode ac characteristics symbol parameter (1) 1. valid for ambient operating temperature: t a = 0 to 70 c; v cc = 4.75 to 5.5 v or 4.5 to 5.5 v (except where noted). m48t58/y unit min max t avav write cycle time 70 ns t avwl address valid to write enable low 0 ns t ave1l address valid to chip enable 1 low 0 ns t ave2h address valid to chip enable 2 high 0 ns t wlwh write enable pulse width 50 ns t e1le1h chip enable 1 low to chip enable 1 high 55 ns t e2he2l chip enable 2 high to chip enable 2 low 55 ns t whax write enable high to address transition 0 ns t e1hax chip enable 1 high to address transition 0 ns t e2lax chip enable 2 low to address transition 0 ns t dvwh input valid to write enable high 30 ns t dve1h input valid to chip enable 1 high 30 ns t dve2l input valid to chip enable 2 low 30 ns t whdx write enable high to input transition 5 ns t e1hdx chip enable 1 high to input transition 5 ns t e2ldx chip enable 2 low to input transition 5 ns t wlqz (2)(3) 2. c l = 5 pf. 3. if e1 goes low or e2 high simultaneously with w going low, the outputs remain in the high impedance state. write enable low to output hi-z 25 ns t avwh address valid to write enable high 60 ns t ave1h address valid to chip enable 1 high 60 ns t ave2l address valid to chip enable 2 low 60 ns t whqx (2)(3) write enable high to output transition 5 ns
data retention mode m48t58, m48t58y 14/33 doc id 2412 rev 7 5 data retention mode with valid v cc applied, the m48t58/y operates as a conventional bytewide? static ram. should the supply voltage decay, the ra m will automatically power-fail deselect, write protecting itself when v cc falls within the v pfd (max), v pfd (min) window. all outputs become high impedance, and all inputs are treated as ?don't care.? note: a power failure during a write cycle may corr upt data at the curren tly addressed location, but does not jeopardize the rest of the ram's content. at voltages below v pfd (min), the user can be assured the memory will be in a write protected state, provided the v cc fall time is not less than t f . the m48t58/y may respond to transient noise spikes on v cc that reach into the deselect window during the time the device is sampling v cc . therefore, decoupling of the power supply lines is recommended. when v cc drops below v so , the control circuit switches power to the internal battery which preserves data and powers the clock. the inte rnal button cell will ma intain data in the m48t58/y for an accumulated period of at least 7 years when v cc is less than v so . as system power returns and v cc rises above v so , the battery is disconnected, and the power supply is switched to external v cc . write protection continues until v cc reaches v pfd (min) plus t rec (min). e1 should be kept high or e2 low as v cc rises past v pfd (min) to prevent inadvertent write cycles prior to system stab ilization. normal ram operation can resume t rec after v cc exceeds v pfd (max). for more information on battery storage life refer to the application note an1012.
m48t58, m48t58y clock operations doc id 2412 rev 7 15/33 6 clock operations 6.1 reading the clock updates to the timekeeper ? registers (see ta bl e 5 ) should be halted before clock data is read to prevent reading data in transition. the biport? timekeeper cells in the ram array are only data registers and not the actual clock counters, so updating the registers can be halted without disturbing the clock itself. updating is halted when a '1' is written to the read bit, d6 in the control register 1ff8h. as long as a '1' remains in that position, updating is halted. after a halt is issued, the registers reflect the count; that is, the day, date, and the time that were current at the moment the halt command was issued. all of the timekeeper register s are updated simult aneously. a halt will not interrupt an update in progress. updating is within a second after the bit is reset to a '0.' 6.2 setting the clock bit d7 of the control register (1ff8h) is the write bit. setting the write bit to a '1,' like the read bit, halts updates to the timekeeper ? registers. the user can then load them with the correct day, date, and time data in 24-hour bcd format (see ta b l e 5 ). resetting the write bit to a '0' then transfers the values of all time registers (1ff9h-1fffh) to the actual timekeeper counters and allows normal operation to resume. the bits marked as '0' in table 5 on page 16 must be written to '0' to a llow for normal timekeeper and ram operation. after the write bit is reset, t he next clock update will oc cur within one second. see the application note an 923 ?timekeeper rolling into the 21st century? for information on century rollover. 6.3 stopping and starting the oscillator the oscillator may be stopped at any time. if the device is going to spend a significant amount of time on the shelf, the oscillator can be turned off to minimize current drain on the battery. the stop bit is the msb of the seconds register. setting it to a '1' stops the oscillator. the m48t58/y is ship ped from stmicroelectronics with the stop bit set to a '1.' when reset to a '0,' the m48t58/y oscillator starts within 1 second.
clock operations m48t58, m48t58y 16/33 doc id 2412 rev 7 table 5. register map keys: s = sign bit ft = frequency test bit r = read bit w = write bit st = stop bit 0 = must be set to '0' ble = battery low enable bit bl = battery low bit (read only) ceb = century enable bit cb = century bit note: when ceb is set to '1,' cb will toggle from '0' to '1' or from '1' to '0' at the turn of the century (dependent upon the initial value set). when ceb is set to '0,' cb will not toggle. the write bit does no t need to be set to write to ceb. 6.4 calibrating the clock the m48t58/y is driven by a quartz-controlled osc illator with a nominal frequency of 32,768 hz. the devices are tested not to exceed 35 ppm (parts per millio n) oscillator frequency error at 25c, which equates to about 1.53 minutes per month. with the calibration bits properly set, the accuracy of each m48t58/y improves to better than +1/?2 ppm at 25c. the oscillation rate of any cryst al changes with temperature (see figure 8 on page 18 ). most clock chips compensate for crystal frequency and temperature shift error with cumbersome ?trim? capacitors. the m48t58/y design, however, employs periodic counter correction. the calibration circuit adds or subt racts counts from the oscillator divider circuit at the divide by 256 stage, as shown in figure 9 on page 18 . the number of times pulses are blanked (subtracted, negative calibration) or split (added, positive calibration) depends upon the value loaded into the five calibration bits found in the control register. adding counts speeds the clock up, subtracting counts slows the clock down. the calibration byte occupies the five lower order bits (d4-d0) in the control register 1ff8h. these bits can be set to represent any value between 0 and 31 in binary form. bit d5 is the address data function/range bcd format d7 d6 d5 d4 d3 d2 d1 d0 1fffh 10 years year year 00-99 1ffeh 0 0 0 10 m month month 01-12 1ffdh ble bl 10 date date date 01-31 1ffch 0 ft ceb cb 0 day century/day 0-1/1-7 1ffbh 0 0 10 hours hours hours 00-23 1ffah 0 10 minutes minutes minutes 00-59 1ff9h st 10 seconds seconds seconds 00-59 1ff8h w r s calibration control
m48t58, m48t58y clock operations doc id 2412 rev 7 17/33 sign bit; '1' indicates positive calibration, '0' indicates negative calibration. calibration occurs within a 64 minute cycle. the first 62 minutes in the cycle may, once per minute, have one second either shortened by 1 28 or lengthened by 2 56 oscillator cycles. if a binary '1' is loaded into the register, only th e first 2 minutes in the 64 minute cycle will be modified; if a binary 6 is loaded, the first 12 will be affected, and so on. therefore, each calibration step has the effect of adding 512 or subtracting 256 oscillator cycles for every 125,829,120 ac tual oscillator cycles, that is +4.068 or ?2.034 ppm of adjustment per calibration step in the calibration register. assu ming that the oscillator is in fact running at exactly 32,768 hz, each of the 31 increments in the calibration byte would represent +10.7 or ?5.35 seconds per month which corresponds to a total range of +5.5 or ? 2.75 minutes per month. two methods are available for ascertaining how much calibration a given m48t58/y may require. the first involves simply setting the cl ock, letting it run for a month and comparing it to a known accurate reference (like wwv broadcasts). while that may seem crude, it allows the designer to give the end user the ability to calibrate hi s clock as his environment may require, even after the final product is packag ed in a non-user serviceable enclosure. all the designer has to do is prov ide a simple utility that ac cesses the calibration byte. the second approach is better suited to a manufacturing environment, and involves the use of some test equipment. when the frequency test (ft) bit (d6 in the day register) is set to a '1,' and d7 of the seconds regist er is a '0' (oscillator running), the frequency test (pin 1) will toggle at 512 hz. any deviation from 512 hz in dicates the degree and direction of oscillator frequency shift at the test temperature. for example, a reading of 512.01024 hz would indicate a +20 ppm oscillator fr equency error, requiring a ?10 (wr001010) to be loaded into the calibration byte for correction. the frequency test pin is an open drain output which requires a pull-up resistor for proper operation. a 500-10 k resistor is recommended in order to control the rise time. for more information on calibration, see application no te an934, ?timekeeper ? calibration.?
clock operations m48t58, m48t58y 18/33 doc id 2412 rev 7 figure 8. crystal accuracy across temperature figure 9. clock calibration ai02124 -80 -60 -100 -40 -20 0 20 0 5 10 15 20 25 30 35 40 45 50 55 60 65 70 f = -0.038 (t - t 0 ) 2 10% f ppm c 2 t 0 = 25 c ppm c ai00594b normal po s itive calibration negative calibration
m48t58, m48t58y clock operations doc id 2412 rev 7 19/33 6.5 battery low flag the m48t58/y automatically performs periodic battery voltage monitoring upon power-up. the battery low flag (bl), bit d6 of the flags register 1ffdh, will be asserted high if the internal or snaphat ? battery is found to be less than approximately 2.5 v and the battery low enable (ble) bit has been previously set to '1.' the bl flag will remain active until completion of battery replacement and subsequent battery low monitoring tests. if a battery low is generated during a power-up sequence, this indicates that the battery voltage is below 2.5 v (approximately), which may be insufficient to main tain data integrity. data should be considered suspect and verified as correct. a fresh battery should be installed. the snaphat top may be replaced while v cc is applied to the device. note: this will cause the clock to lose time during the interval the snaphat ? battery/crystal top is disconnected. note: battery monitoring is a useful technique only when performed periodically. the m48t58/y only monitors the battery when a nominal v cc is applied to the devi ce. thus applications which require extensive durations in the battery back-up mode should be powered-up periodically (at least once every few months) in order for this technique to be beneficial. additionally, if a battery low is indicated, data integrity should be verified upon power-up via a checksum or other technique. 6.6 century bit bit d5 and d4 of clock register 1ffch contain the century enable bit (ceb) and the century bit (cb). setting ceb to a '1' will cause cb to toggle, either from a '0' to '1' or from '1' to '0' at the turn of the century (depending upon its initial state). if ceb is set to a '0,' cb will not toggle. note: the write bit must be set in order to write to the century bit.
clock operations m48t58, m48t58y 20/33 doc id 2412 rev 7 6.7 v cc noise and negative going transients i cc transients, including those produced by output switching, can produce voltage fluctuations, resulting in spikes on the v cc bus. these transients can be reduced if capacitors are used to store energy which stabilizes the v cc bus. the energy stored in the bypass capacitors will be released as low goin g spikes are generated or energy will be absorbed when overshoots occur. a bypass capacitor value of 0.1 f (as shown in figure 10 ) is recommended in order to provide the needed filtering. in addition to transients that are caused by normal sram operation, power cycling can generate negative voltage spikes on v cc that drive it to values below v ss by as much as one volt. these negative spikes can cause data corruption in the sram while in battery backup mode. to protect from these voltage spikes, it is recommended to connect a schottky diode from v cc to v ss (cathode connected to v cc , anode to v ss ). schottky diode 1n5817 is recommended for through hole and mbrs120t3 is recommended for surface mount. figure 10. supply voltage protection ai02169 v cc 0.1 f device v cc v ss
m48t58, m48t58y maximum ratings doc id 2412 rev 7 21/33 7 maximum ratings stressing the device above the rating listed in the absolute maximum ratings table may cause permanent damage to the device. these are stress ratings only and operation of the device at these or any other conditions above those indicated in the operating sections of this specification is not imp lied. exposure to absolute ma ximum rating conditions for extended periods may affect device reliability. table 6. absolute maximum ratings caution: negative undershoots below ?0.3 v are not allowed on any pin while in the battery backup mode. caution: do not wave solder soic to avoid damaging snaphat ? sockets. symbol parameter value unit t a ambient operating temperature 0 to 70 c t stg storage temperature (v cc off, oscillator off) ?40 to 85 c t sld (1)(2)(3) 1. for dip package, soldering temperature of the ic leads is to not exceed 260 c for 10 seconds. in order to protect the lithium battery, preheat temperatures must be limited such that the battery temperature does not exceed +85 c. furthermore, the devic es shall not be exposed to ir reflow. 2. for dip packaged devices, ul trasonic vibrations should not be used for post-solder cleaning to avoid damaging the crystal. 3. for soh28 package, lead-free (pb- free) lead finish: reflow at peak temperature of 260c (the time above 255c must not exceed 30 seconds). lead solder temperature for 10 seconds 260 c v io input or output voltages ?0.3 to 7 v v cc supply voltage ?0.3 to 7 v i o output current 20 ma p d power dissipation 1 w
dc and ac parameters m48t58, m48t58y 22/33 doc id 2412 rev 7 8 dc and ac parameters this section summarizes the operating and measurement conditions, as well as the dc and ac characteristics of the device. the parameters in the following dc and ac characteristic tables are derived from tests performed under the measurement conditions listed in ta bl e 7 . designers should check that the operating conditions in their projects match the measurement conditions when using the quoted parameters. table 7. operating and ac measurement conditions note: output hi-z is defined as the point where data is no longer driven. figure 11. ac measurement load circuit table 8. capacitance parameter m48t58 m48t58y unit supply voltage (v cc ) 4.75 to 5.5 4.5 to 5.5 v ambient operating temperature (t a ) 0 to 70 0 to 70 c load capacitance (c l )100100pf input rise and fall times 5 5ns input pulse voltages 0 to 3 0 to 3 v input and output timing ref. voltages 1.5 1.5 v symbol parameter (1)(2) 1. effective capacitance m easured with power supply at 5 v; sampled only, not 100% tested. 2. at 25 c, f = 1 mhz. min max unit c in input capacitance - 10 pf c out (3) 3. outputs deselected. output capacitance - 10 pf ai010 3 0 5v out c l = 100pf or 5pf c l incl u de s jig c a p a cit a nce 1.9k device under te s t 1k
m48t58, m48t58y dc and ac parameters doc id 2412 rev 7 23/33 table 9. dc characteristics figure 12. power down/up mode ac waveforms symbol parameter test condition (1) 1. valid for ambient operating temperature: t a = 0 to 70 c; v cc = 4.75 to 5.5 v or 4.5 to 5.5 v (except where noted). m48t58 m48t58y unit min max min max i li input leakage current 0 v v in v cc 1 1 a i lo (2) 2. outputs deselected. output leakage current 0 v v out v cc 1 1 a i cc supply current outputs open 50 50 ma i cc1 supply current (standby) ttl e1 = v ih e2 = v io 33ma i cc2 supply current (standby) cmos e1 = v cc ? 0.2 v e2 = v ss + 0.2 v 33ma v il input low voltage ?0.3 0.8 ?0.3 0.8 v v ih input high voltage 2.2 v cc + 0.3 2.2 v cc + 0.3 v v ol output low voltage i ol = 2.1 ma 0.4 0.4 output low voltage (ft) (3) 3. the ft pin is open drain. i ol = 10 ma 0.4 0.4 v v oh output high voltage i oh = ?1 ma 2.4 2.4 v ai01168c v cc inputs (per control input) outputs don't care high-z tf tfb tr tpd trb tdr valid valid (per control input) recognized recognized v pfd (max) v pfd (min) v so trec
dc and ac parameters m48t58, m48t58y 24/33 doc id 2412 rev 7 table 10. power down/up ac characteristics table 11. power down/up trip points dc characteristics symbol parameter (1) 1. valid for ambient operating temperature: t a = 0 to 70 c; v cc = 4.75 to 5.5 v or 4.5 to 5.5 v (except where noted). min max unit t pd e1 or w at v ih or e2 at v il before power down 0 s t f (2) 2. v pfd (max) to v pfd (min) fall time of less than t f may result in deselection/write protection not occurring until 200 s after v cc passes v pfd (min). v pfd (max) to v pfd (min) v cc fall time 300 s t fb (3) 3. v pfd (min) to v ss fall time of less than t fb may cause corruption of ram data. v pfd (min) to v ss v cc fall time m48t58 10 s m48t58y 10 s t r v pfd (min) to v pfd (max) v cc rise time 10 s t rb v ss to v pfd (min) v cc rise time 1 s t rec v pfd (max) to inputs recognized 40 200 ms symbol parameter (1)(2) 1. valid for ambient operating temperature: t a = 0 to 70 c; v cc = 4.75 to 5.5 v or 4.5 to 5.5 v (except where noted). 2. all voltages referenced to v ss . min typ max unit v pfd power-fail deselect voltage m48t58 4.5 4.6 4.75 v m48t58y 4.2 4.35 4.5 v v so battery backup switchover voltage 3.0 v t dr (3) 3. at 25 c, v cc = 0 v. expected data retention time 7 years
m48t58, m48t58y package mechanical data doc id 2412 rev 7 25/33 9 package mechanical data in order to meet environmental requirements, st offers these devices in different grades of ecopack ? packages, depending on their level of environmental compliance. ecopack ? specifications, grade definitions and product status are available at: www.st.com . ecopack ? is an st trademark. figure 13. pcdip28 ? 28-pin plastic dip, battery caphat?, package outline note: drawing is not to scale. table 12. pcdip28 ? 28-pin plastic dip, battery caphat?, package mech. data pcdip a2 a1 a l b1 b e1 d e n 1 c ea e 3 symb mm inches typ min max typ min max a 8.89 9.65 0.350 0.380 a1 0.38 0.76 0.015 0.030 a2 8.38 8.89 0.330 0.350 b 0.38 0.53 0.015 0.021 b1 1.14 1.78 0.045 0.070 c 0.20 0.31 0.008 0.012 d 39.37 39.88 1.550 1.570 e 17.83 18.34 0.702 0.722 e1 2.29 2.79 0.090 0.110 e3 33.02 1.3 ea 15.24 16.00 0.600 0.630 l 3.05 3.81 0.120 0.150 n28 28
package mechanical data m48t58, m48t58y 26/33 doc id 2412 rev 7 figure 14. soh28 ? 28-lead plastic small outline, 4-socket battery snaphat ? , package outline note: drawing is not to scale. s oh-a e n d c l a1 a 1 h a cp be a2 eb table 13. soh28 ? 28-lead plastic small outline, 4-socket battery snaphat ? , package mech. data symb mm inches typ min max typ min max a3.050.120 a1 0.05 0.36 0.002 0.014 a2 2.34 2.69 0.092 0.106 b 0.36 0.51 0.014 0.020 c 0.15 0.32 0.006 0.012 d 17.71 18.49 0.697 0.728 e 8.23 8.89 0.324 0.350 e1.27? ?0.050? ? eb 3.20 3.61 0.126 0.142 h 11.51 12.70 0.453 0.500 l 0.41 1.27 0.016 0.050 a 08 08 n28 28 cp 0.10 0.004
m48t58, m48t58y package mechanical data doc id 2412 rev 7 27/33 figure 15. sh ? 4-pin snaphat ? housing for 48 mah battery & crystal, pack. outline note: drawing is not to scale. s htk-a a1 a d e ea eb a2 b l a 3 table 14. sh ? 4-pin snaphat ? housing for 48 mah battery & crystal, package mech. data symb mm inches typ min max typ min max a9.780.385 a1 6.73 7.24 0.265 0.285 a2 6.48 6.99 0.255 0.275 a3 0.38 0.015 b 0.46 0.56 0.018 0.022 d 21.21 21.84 0.835 0.860 e 14.22 14.99 0.560 0.590 ea 15.55 15.95 0.612 0.628 eb 3.20 3.61 0.126 0.142 l 2.03 2.29 0.080 0.090
package mechanical data m48t58, m48t58y 28/33 doc id 2412 rev 7 figure 16. sh ? 4-pin snaphat ? housing for 120 mah battery & crystal, package outline note: drawing is not to scale. s htk-a a1 a d e ea eb a2 b l a 3 table 15. sh ? 4-pin snaphat ? housing for 120 mah battery & crystal, package mech. data symb mm inches typ min max typ min max a 10.54 0.415 a1 8.00 8.51 0.315 0.335 a2 7.24 8.00 0.285 0.315 a3 0.38 0.015 b 0.46 0.56 0.018 0.022 d 21.21 21.84 0.835 0.860 e 17.27 18.03 0.680 0.710 eb 3.20 3.61 0.126 0.142 l 2.03 2.29 0.080 0.090
m48t58, m48t58y part numbering doc id 2412 rev 7 29/33 10 part numbering table 16. ordering information scheme caution: do not place the snaphat ? battery package ?m4txx-br12sh? in conductive foam as it will drain the lithium button-cell battery. for other options, or for more information on any aspect of this device, please contact the st sales office nearest you. example: m48t 58 ?70 mh 1 e device type m48t supply voltage and write protect voltage 58 (1) = v cc = 4.75 to 5.5 v; v pfd = 4.5 to 4.75 v 1. the m48t58 part is offered with the pcdip28 (e.g., caphat?) package only. 58y = v cc = 4.5 to 5.5 v; v pfd = 4.2 to 4.5 v speed ?70 = 70 ns package pc = pcdip28 mh (2) = soh28 2. the soic package (soh28) requires the snaphat ? battery package which is ordered separately under the part number ?m4txx-br12sh? in plastic tube or ?m4txx-br12shtr? in tape & reel form (see table 17 ). temperature range 1 = 0 to 70c shipping method for soh28: blank = tubes (not for new design - use e) e = lead-free package (ecopack ? ), tubes f = lead-free package (ecopack ? ), tape & reel tr = tape & reel (not for new design - use f) for pcdip28: blank = tubes
part numbering m48t58, m48t58y 30/33 doc id 2412 rev 7 table 17. snaphat ? battery table part number description package m4t28-br12sh lithium battery (48 mah) snaphat ? sh m4t32-br12sh lithium battery (120 mah) snaphat ? sh
m48t58, m48t58y environmental information doc id 2412 rev 7 31/33 11 environmental information figure 17. recycling symbols this product contains a non-rechargeable lithi um (lithium carbon monofluoride chemistry) button cell battery fully encapsulated in the final product. recycle or dispose of batteries in accordance with the battery manufacturer's instructions and local/national disposal and recycling regulations. please refer to the following web site address for additional information regarding compliance statements and waste recycling. go to www.st.com/rtc , then select "lithium battery recycling" from "related topics".
revision history m48t58, m48t58y 32/33 doc id 2412 rev 7 12 revision history table 18. document revision history date revision changes jul-1999 1 first issue 27-jul-2000 1.1 century bit and battery low flag paragraphs added; power down/up ac characteristics table and waveforms changed ( ta bl e 1 0 , figure 12 ) 04-jun-2001 2 reformatted; temperature information added ( ta b l e 9 , 3 , 4 , 10 , 11 ) 31-jul-2001 2.1 formatting changes from recent document review findings 20-may-2002 2.2 modify reflow time and temperature footnotes ( ta bl e 6 ) 01-apr-2003 3 v2.2 template a pplied; test condition updated ( ta b l e 1 1 ) 17-jul-2003 3.1 update ?battery low flag? information 02-apr-2004 4 reformatted; update lead-free packaging information ( ta b l e 6 , 16 ) 30-aug-2007 5 reformatted; added lead-free second level interconnect information to cover page and section 9: package mechanical data ; updated ta bl e 9 . 24-mar-2009 6 updated ta b l e 6 , section 9: package mechanical data ; added section 11: environmental information ; minor reformatting. 02-aug-2010 7 reformatted document; updated section 7 , ta b l e 1 2 .
m48t58, m48t58y doc id 2412 rev 7 33/33 please read carefully: information in this document is provided solely in connection with st products. stmicroelectronics nv and its subsidiaries (?st ?) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described he rein at any time, without notice. all st products are sold pursuant to st?s terms and conditions of sale. purchasers are solely responsible for the choice, selection and use of the st products and services described herein, and st as sumes no liability whatsoever relating to the choice, selection or use of the st products and services described herein. no license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted under this document. i f any part of this document refers to any third party products or services it shall not be deemed a license grant by st for the use of such third party products or services, or any intellectual property contained therein or considered as a warranty covering the use in any manner whatsoev er of such third party products or services or any intellectual property contained therein. unless otherwise set forth in st?s terms and conditions of sale st disclaims any express or implied warranty with respect to the use and/or sale of st products including without limitation implied warranties of merchantability, fitness for a parti cular purpose (and their equivalents under the laws of any jurisdiction), or infringement of any patent, copyright or other intellectual property right. unless expressly approved in writing by an authorized st representative, st products are not recommended, authorized or warranted for use in milita ry, air craft, space, life saving, or life sustaining applications, nor in products or systems where failure or malfunction may result in personal injury, death, or severe property or environmental damage. st products which are not specified as "automotive grade" may only be used in automotive applications at user?s own risk. resale of st products with provisions different from the statements and/or technical features set forth in this document shall immediately void any warranty granted by st for the st product or service described herein and shall not create or extend in any manner whatsoev er, any liability of st. st and the st logo are trademarks or registered trademarks of st in various countries. information in this document supersedes and replaces all information previously supplied. the st logo is a registered trademark of stmicroelectronics. all other names are the property of their respective owners. ? 2010 stmicroelectronics - all rights reserved stmicroelectronics group of companies australia - belgium - brazil - canada - china - czech republic - finland - france - germany - hong kong - india - israel - ital y - japan - malaysia - malta - morocco - philippines - singapore - spain - sweden - switzerland - united kingdom - united states of america www.st.com

▲Up To Search▲

Price & Availability of M48T58Y-70PC1

	To Download M48T58Y-70PC1 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .